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DAC
2006
ACM
14 years 2 months ago
Modeling and minimization of PMOS NBTI effect for robust nanometer design
Negative bias temperature instability (NBTI) has become the dominant reliability concern for nanoscale PMOS transistors. In this paper, a predictive model is developed for the deg...
Rakesh Vattikonda, Wenping Wang, Yu Cao
ICCAD
1996
IEEE
87views Hardware» more  ICCAD 1996»
14 years 29 days ago
Partitioned ROBDDs - a compact, canonical and efficiently manipulable representation for Boolean functions
We presenta new representationfor Boolean functions called PartitionedROBDDs. In this representation we divide the Boolean space into `k' partitions and represent a function ...
Amit Narayan, Jawahar Jain, Masahiro Fujita, Alber...
FDTC
2006
Springer
117views Cryptology» more  FDTC 2006»
14 years 14 days ago
DPA on Faulty Cryptographic Hardware and Countermeasures
Abstract. Balanced gates are an effective countermeasure against power analysis attacks only if they can be guaranteed to maintain their power balance. Traditional testing and reli...
Konrad J. Kulikowski, Mark G. Karpovsky, Alexander...
TVLSI
2008
153views more  TVLSI 2008»
13 years 8 months ago
Characterization of a Novel Nine-Transistor SRAM Cell
Data stability of SRAM cells has become an important issue with the scaling of CMOS technology. Memory banks are also important sources of leakage since the majority of transistors...
Zhiyu Liu, Volkan Kursun
ET
2010
98views more  ET 2010»
13 years 7 months ago
MONSOON: SAT-Based ATPG for Path Delay Faults Using Multiple-Valued Logics
Abstract As technology scales down into the nanometer era, delay testing of modern chips has become more and more important. Tests for the path delay fault model are widely used to...
Stephan Eggersglüß, Görschwin Fey,...