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» Verifying VLSI Circuits
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VLSID
2002
IEEE
189views VLSI» more  VLSID 2002»
14 years 9 months ago
Automatic Modeling and Validation of Pipeline Specifications Driven by an Architecture Description Language
Verification is one of the most complex and expensive tasks in the current Systems-on-Chip (SOC) design process. Many existing approaches employ a bottom-up approach to pipeline v...
Prabhat Mishra, Hiroyuki Tomiyama, Ashok Halambi, ...
DFT
2007
IEEE
142views VLSI» more  DFT 2007»
14 years 3 months ago
Quantitative Analysis of In-Field Defects in Image Sensor Arrays
Growth of pixel density and sensor array size increases the likelihood of developing in-field pixel defects. An ongoing study on defect development in imagers has now provided us ...
Jenny Leung, Jozsef Dudas, Glenn H. Chapman, Israe...
ITNG
2007
IEEE
14 years 3 months ago
On Design and Analysis of a Feasible Network-on-Chip (NoC) Architecture
In this paper, we present several enhanced network techniques which are appropriate for VLSI implementation and have reduced complexity, high throughput, and simple routing algori...
Jun Ho Bahn, Seung Eun Lee, Nader Bagherzadeh
IJCM
2002
73views more  IJCM 2002»
13 years 8 months ago
Space-Time Equations for Non-Unimodular Mappings
Abstract. The class of systems of uniform recurrence equations (UREs) is closed under unimodular transformations. As a result, every systolic array described by a unimodular mappin...
Jingling Xue, Patrick M. Lenders
ICIP
2004
IEEE
14 years 10 months ago
An implemented architecture of deblocking filter for H.264/AVC
H.264/AVC is a new international standard for the compression of natural video images, in which a deblocking filter has been adopted to remove blocking artifacts. In this paper, w...
Bin Sheng, Wen Gao, Di Wu