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» Verifying VLSI Circuits
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DFT
2009
IEEE
155views VLSI» more  DFT 2009»
14 years 3 months ago
Errors in DNA Self-Assembly by Synthesized Tile Sets
This paper presents a study of errors that occur in DNA self-assembly using synthesized tile sets for template manufacturing. It is shown that due to the reduced size, aggregates ...
Xiaojun Ma, Masoud Hashempour, Yong-Bin Kim, Fabri...
ESA
2009
Springer
149views Algorithms» more  ESA 2009»
14 years 3 months ago
Sparse Cut Projections in Graph Streams
Finding sparse cuts is an important tool for analyzing large graphs that arise in practice, such as the web graph, online social communities, and VLSI circuits. When dealing with s...
Atish Das Sarma, Sreenivas Gollapudi, Rina Panigra...
DATE
2008
IEEE
161views Hardware» more  DATE 2008»
14 years 3 months ago
Spatial Correlation Extraction via Random Field Simulation and Production Chip Performance Regression
Statistical timing analysis needs a priori knowledge of process variations. Lack of such a priori knowledge of process variations prevents accurate statistical timing analysis, fo...
Bao Liu
DFT
2008
IEEE
120views VLSI» more  DFT 2008»
14 years 3 months ago
Built-in-Self-Diagnostics for a NoC-Based Reconfigurable IC for Dependable Beamforming Applications
Integrated circuits (IC) targeting at the streaming applications for tomorrow are becoming a fast growing market. Applications such as beamforming require mass computing capabilit...
Oscar Kuiken, Xiao Zhang, Hans G. Kerkhoff
RECONFIG
2008
IEEE
224views VLSI» more  RECONFIG 2008»
14 years 3 months ago
Automatic Construction of Large-Scale Regular Expression Matching Engines on FPGA
—We present algorithms for implementing large-scale regular expression matching (REM) on FPGA. Based on the proposed algorithms, we develop tools that first transform regular ex...
Yi-Hua E. Yang, Viktor K. Prasanna