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» Verifying VLSI Circuits
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120
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ISPD
2003
ACM
151views Hardware» more  ISPD 2003»
15 years 8 months ago
Capturing crosstalk-induced waveform for accurate static timing analysis
We propose a method to capture crosstalk-induced noisy waveform for crosstalk-aware static timing analysis. The effects of capacitive coupling noise on timing are conventionally m...
Masanori Hashimoto, Yuji Yamada, Hidetoshi Onodera
PADS
2003
ACM
15 years 8 months ago
DVS: An Object-Oriented Framework for Distributed Verilog Simulation
There is a wide-spread usage of hardware design languages(HDL) to speed up the time-to-market for the design of modern digital systems. Verification engineers can simulate hardwa...
Lijun Li, Hai Huang, Carl Tropper
165
Voted
FPGA
2003
ACM
161views FPGA» more  FPGA 2003»
15 years 8 months ago
Implementation of BEE: a real-time large-scale hardware emulation engine
This paper describes the hardware implementation of a real-time, large-scale, multi-chip FPGA (Field Programmable Gate Array) based emulation engine with a capacity of 10 million ...
Chen Chang, Kimmo Kuusilinna, Brian C. Richards, R...
DATE
2010
IEEE
134views Hardware» more  DATE 2010»
15 years 8 months ago
Pseudo-CMOS: A novel design style for flexible electronics
Flexible electronics have attracted much attention since they enable promising applications such as lowcost RFID tags and e-paper. Thin-film transistors (TFTs) are considered as ...
Tsung-Ching Huang, Kenjiro Fukuda, Chun-Ming Lo, Y...
101
Voted
ISLPED
2000
ACM
70views Hardware» more  ISLPED 2000»
15 years 7 months ago
An adaptive on-chip voltage regulation technique for low-power applications
In this paper we present a completely on-chip voltage regulation technique which promises to adjust the degree of voltage regulation in a digital logic chip in the face of process...
Nicola Dragone, Akshay Aggarwal, L. Richard Carley