1093 search results - page 207 / 219 » Verifying VLSI Circuits |
TABLEAUX
1998
Springer
13 years 11 months ago
1998
Springer
ple (Extended Abstract) Edmund M. Clarke and Sergey Berezin Carnegie Mellon University -- USA Model checking is an automatic verification technique for finite state concurrent syst...
TACAS
1998
Springer
13 years 11 months ago
1998
Springer
This paper enables symbolic ternary simulation of systems with large embedded memories. Each memory array is replaced with a behavioral model, where the number of symbolic variable...
DAC
1997
ACM
13 years 11 months ago
1997
ACM
Cr, As the complexity of high-performance microprocessor increases, functional verification becomes more and more difficult and RTL simulation emerges as the bottleneck of the des...
ICCAD
1996
IEEE
13 years 11 months ago
1996
IEEE
Functional simulation is the most widely used method for design verification. At various levels of abstraction, e.g., behavioral, register-transfer level and gate level, the design...
EURODAC
1994
IEEE
13 years 11 months ago
1994
IEEE
Abstract -- A general framework for synthesis of asynchronous control circuits at the state graph level is proposed. The framework can consider both concurrency reduction as well a...