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» Verifying VLSI Circuits
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DFT
2006
IEEE
122views VLSI» more  DFT 2006»
14 years 13 days ago
Efficient and Robust Delay-Insensitive QCA (Quantum-Dot Cellular Automata) Design
The concept of clocking for QCA, referred to as the four-phase clocking, is widely used. However, inherited characteristics of QCA, such as the way to hold state, the way to synch...
Minsu Choi, Myungsu Choi, Zachary D. Patitz, Nohpi...
FCCM
2004
IEEE
101views VLSI» more  FCCM 2004»
14 years 15 days ago
Secure Remote Control of Field-programmable Network Devices
A circuit and an associated lightweight protocol have been developed to secure communication between a control console and remote programmable network devices1 . The circuit provi...
Haoyu Song, Jing Lu, John W. Lockwood, James Mosco...
GLVLSI
1999
IEEE
92views VLSI» more  GLVLSI 1999»
14 years 1 months ago
Fault Coverage Estimation for Early Stage of VLSI Design
This paper proposes a new fault coverage estimation model which can be used in the early stage of VLSI design. The fault coverage model is an exponentially decaying function with ...
Von-Kyoung Kim, Tom Chen, Mick Tegethoff
DAC
2006
ACM
14 years 9 months ago
Are carbon nanotubes the future of VLSI interconnections?
Increasing resistivity of copper with scaling and rising demands on current density requirements are driving the need to identify new wiring solutions for deep nanometer scale VLS...
Kaustav Banerjee, Navin Srivastava
DFT
2006
IEEE
82views VLSI» more  DFT 2006»
14 years 2 months ago
VLSI Implementation of a Fault-Tolerant Distributed Clock Generation
In this paper we will introduce a novel approach for the on-chip generation of a faulttolerant clock. We will motivate why it becomes more and more desirable to provide VLSI circu...
Markus Ferringer, Gottfried Fuchs, Andreas Steinin...