1093 search results - page 55 / 219 » Verifying VLSI Circuits |
GLVLSI
2006
IEEE
14 years 4 months ago
2006
IEEE
This paper presents a systematic design methodology for yield enhancement of asynchronous logic circuits using 3-D (3-Dimensional) integration technology. In this design, the targ...
DFT
2002
IEEE
14 years 2 months ago
2002
IEEE
Concurrent error detection (CED) methods are typically employed to provide an indication of the operational health of synchronous circuits during normal functionality. Existing CE...
VLSID
1997
IEEE
14 years 2 months ago
1997
IEEE
The problem of test generation belongs to the class of NP-complete problems and it is becoming more and more di cult as the complexity of VLSI circuits increases, and as long as e...
GLVLSI
2005
IEEE
14 years 3 months ago
2005
IEEE
The ever-increasing number of transistors on a chip has resulted in very large scale integration (VLSI) systems whose performance and manufacturing costs are driven by on-chip wir...
ISLPED
1997
ACM
14 years 1 months ago
1997
ACM
With the advent of portable and high density microelectronic devices, the power dissipation of VLSI circuits is becoming a critical concern. In this paper, we propose a post