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» Verifying VLSI Circuits
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VLSID
1999
IEEE
97views VLSI» more  VLSID 1999»
14 years 2 months ago
A New Methodology for Concurrent Technology Development and Cell Library Optimization
To minimize the time to market and cost of new sub 0.25um process technologies and products, PDF Solutions, Inc., has developed a new comprehensive approach based on the use of pr...
Marko P. Chew, Sharad Saxena, Thomas F. Cobourn, P...
DFT
2008
IEEE
182views VLSI» more  DFT 2008»
13 years 11 months ago
Hardware Trojan Detection and Isolation Using Current Integration and Localized Current Analysis
This paper addresses a new threat to the security of integrated circuits (ICs). The migration of IC fabrication to untrusted foundries has made ICs vulnerable to malicious alterat...
Xiaoxiao Wang, Hassan Salmani, Mohammad Tehranipoo...
VLSID
2002
IEEE
94views VLSI» more  VLSID 2002»
14 years 10 months ago
Timing Yield Calculation Using an Impulse-Train Approach
This paper presents a new method to compute the probability distribution of the delay of a combinational circuit and uses it obtain an estimate of the yield of the process that ma...
Srinath R. Naidu
DATE
2006
IEEE
89views Hardware» more  DATE 2006»
14 years 4 months ago
A practical method to estimate interconnect responses to variabilities
Variabilities in metal interconnect structures can affect circuit timing performance or even cause function failure in VLSI designs. This paper proposes a method to estimate the ...
Frank Liu
DFT
2005
IEEE
110views VLSI» more  DFT 2005»
14 years 3 months ago
A design flow for protecting FPGA-based systems against single event upsets
SRAM-based Field Programmable Gate Arrays (FPGAs) are very susceptible to Single Event Upsets (SEUs) that may have dramatic effects on the circuits they implement. In this paper w...
Luca Sterpone, Massimo Violante