1093 search results - page 64 / 219 » Verifying VLSI Circuits |
VLSID
2005
IEEE
14 years 10 months ago
2005
IEEE
The electromigration effect within current-density-stressed signal and power lines is an ubiquitous and increasingly important reliability and design problem in sub-micron IC desi...
ICCAD
1996
IEEE
14 years 2 months ago
1996
IEEE
This paper presents a new framework for formal logic verification. What is depicted here is fundamentally different from previous approaches. In earlier approaches, the circuit is ...
ISCAS
2003
IEEE
14 years 3 months ago
2003
IEEE
Experimental results characterizing a VLSI multi-channel potentiostat sensor system designed for sensing distributed neurotransmitter activity are presented. Neurotransmitter conc...
DAC
2005
ACM
14 years 11 months ago
2005
ACM
el Predicate Abstraction and Refinement for Verifying RTL Verilog Himanshu Jain CMU SCS, Pittsburgh, PA 15213 Daniel Kroening ETH Z?urich, Switzerland Natasha Sharygina CMU SCS an...
GLVLSI
2003
IEEE
14 years 3 months ago
2003
IEEE
Clock-delayed (CD) domino is a dynamic logic family developed to provide both inverting and non-inverting logic on single-rail gates. It is self-timed and can be easily pipelined ...