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» Verifying VLSI Circuits
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VTS
2003
IEEE
115views Hardware» more  VTS 2003»
14 years 3 months ago
Fault Testing for Reversible Circuits
Irreversible computation necessarily results in energy dissipation due to information loss. While small in comparison to the power consumption of today’s VLSI circuits, if curre...
Ketan N. Patel, John P. Hayes, Igor L. Markov
SBCCI
2003
ACM
160views VLSI» more  SBCCI 2003»
14 years 3 months ago
Novel Design Methodology for High-Performance XOR-XNOR Circuit Design
As we scale down to deep submicron (DSM) technology, noise is becoming a metric of equal importance as power, speed, and area. Smaller feature sizes, low voltage, and high frequen...
Sumeer Goel, Mohamed A. Elgamel, Magdy A. Bayoumi
GLVLSI
2003
IEEE
185views VLSI» more  GLVLSI 2003»
14 years 3 months ago
Noise tolerant low voltage XOR-XNOR for fast arithmetic
With scaling down to deep submicron and nanometer technologies, noise immunity is becoming a metric of the same importance as power, speed, and area. Smaller feature sizes, low vo...
Mohamed A. Elgamel, Sumeer Goel, Magdy A. Bayoumi
ISVLSI
2002
IEEE
129views VLSI» more  ISVLSI 2002»
14 years 2 months ago
Accelerating Retiming Under the Coupled-Edge Timing Model
Retiming has been shown to be a powerful technique for improving the performance of synchronous circuits. However, even though retiming algorithms of polynomial time complexity ha...
Ingmar Neumann, Kolja Sulimma, Wolfgang Kunz
DFT
2005
IEEE
90views VLSI» more  DFT 2005»
14 years 3 months ago
On the Modeling and Analysis of Jitter in ATE Using Matlab
This paper presents a new jitter component analysis method for mixed mode VLSI chip testing in Automatic Test Equipment (ATE). The separate components are analyzed individually an...
Kyung Ki Kim, Jing Huang, Yong-Bin Kim, Fabrizio L...