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» Verifying VLSI Circuits
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ISCAS
2008
IEEE
170views Hardware» more  ISCAS 2008»
14 years 4 months ago
Integrated circuit implementation of a cortical neuron
— This paper presents an analogue integrated circuit implementation of a cortical neuron model. The VLSI chip prototype has been implemented in a 0.35 µm CMOS technology. The si...
Jayawan H. B. Wijekoon, Piotr Dudek
ISCAS
1999
IEEE
110views Hardware» more  ISCAS 1999»
14 years 2 months ago
Noise-tolerant dynamic circuit design
-- Noise in deep submicron technology combined with the move towards dynamic circuit techniques for higher performance have raised concerns about reliability and energyefficiency o...
Lei Wang, Naresh R. Shanbhag
VLSID
2000
IEEE
135views VLSI» more  VLSID 2000»
14 years 1 months ago
Performance and Functional Verification of Microprocessors
We address the problem of verifying the correctness of pre-silicon models of a microprocessor. We touch on the latest advances in this area by considering two different aspects of...
Pradip Bose, Jacob A. Abraham
ARVLSI
1999
IEEE
162views VLSI» more  ARVLSI 1999»
14 years 2 months ago
Conjunction Search Using a 1-D, Analog VLSI-based, Attentional Search/Tracking Chip
The ability of animals to select a limited region of sensory space for scrutiny is an important factor in dealing with cluttered or complex sensory environments. Such an attention...
Timothy K. Horiuchi, Ernst Niebur
SPAA
2000
ACM
14 years 1 months ago
Compact, multilayer layout for butterfly fat-tree
Modern VLSI processing supports a two-dimensional surface for active devices along with multiple stacked layers of interconnect. With the advent of planarization, the number of la...
André DeHon