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» Verifying VLSI Circuits
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DATE
1999
IEEE
120views Hardware» more  DATE 1999»
14 years 2 months ago
FreezeFrame: Compact Test Generation Using a Frozen Clock Strategy
Test application time is an important factor in the overall cost of VLSI chip testing. We present a new ATPG approach for generating compact test sequences for sequential circuits...
Yanti Santoso, Matthew C. Merten, Elizabeth M. Rud...
VLSID
2007
IEEE
131views VLSI» more  VLSID 2007»
14 years 4 months ago
A Placement Methodology for Robust Clocking
As the VLSI technology scales towards the nanometer regime, circuit performance is increasingly affected by variations. These variations need to be considered at an early stage in...
Ganesh Venkataraman, Jiang Hu
GLVLSI
2006
IEEE
120views VLSI» more  GLVLSI 2006»
14 years 4 months ago
Sensitivity evaluation of global resonant H-tree clock distribution networks
A sensitivity analysis of resonant H-tree clock distribution networks is presented in this paper for a TSMC 0.18 μm CMOS technology. The analysis focuses on the effect of the dri...
Jonathan Rosenfeld, Eby G. Friedman
GLVLSI
2005
IEEE
83views VLSI» more  GLVLSI 2005»
14 years 3 months ago
Diagnosing multiple transition faults in the absence of timing information
As timing requirements in today’s advanced VLSI designs become more aggressive, the need for automated tools to diagnose timing failures increases. This work presents two such a...
Jiang Brandon Liu, Magdy S. Abadir, Andreas G. Ven...
GLVLSI
2003
IEEE
166views VLSI» more  GLVLSI 2003»
14 years 3 months ago
Exponential split accumulator for high-speed reduced area low-power direct digital frequency synthesizers
A new split accumulator architecture to be used in direct digital frequency synthesizers (DDFS) systems is presented. This new design eliminates the need of adders on the section ...
Edward Merlo, Kwang-Hyun Baek, Myung-Jun Choe