Sciweavers

1093 search results - page 86 / 219
» Verifying VLSI Circuits
Sort
View
VLSID
1997
IEEE
112views VLSI» more  VLSID 1997»
14 years 2 months ago
Adder and Comparator Synthesis with Exclusive-OR Transform of Inputs
An exclusive-OR transform of input variables significantly reduces the size of the PLA implementation for adder and comparator circuits. For n bit adder circuits, the size of PLA ...
James Jacob, P. Srinivas Sivakumar, Vishwani D. Ag...
GLVLSI
2007
IEEE
173views VLSI» more  GLVLSI 2007»
13 years 10 months ago
Modeling and estimating leakage current in series-parallel CMOS networks
This paper reviews the modeling of subthreshold leakage current and proposes an improved model for general series-parallel CMOS networks. The presence of on-switches in off-networ...
Paulo F. Butzen, André Inácio Reis, ...
GLVLSI
2008
IEEE
197views VLSI» more  GLVLSI 2008»
13 years 10 months ago
Efficient tree topology for FPGA interconnect network
This paper presents an improved Tree-based architecture that unifies two unidirectional programmable networks: A predictible downward network based on the Butterfly-FatTree topolo...
Zied Marrakchi, Hayder Mrabet, Emna Amouri, Habib ...
VLSID
2002
IEEE
107views VLSI» more  VLSID 2002»
14 years 10 months ago
Estimation of Maximum Power-Up Current
Power gating is emerging as a viable solution to reduction of leakage current. However, power gated circuits are different from the conventional designs in the sense that a power-...
Fei Li, Lei He, Kewal K. Saluja
AIA
2007
13 years 11 months ago
Minimizing leakage: What if every gate could have its individual threshold voltage?
Designers aim at fast but low-power consuming integrated circuits. Since high processing speed always comes with high energy demands, the literature provides several ways to reduc...
Ralf Salomon, Frank Sill, Dirk Timmermann