1093 search results - page 96 / 219 » Verifying VLSI Circuits |
VLSID
2003
IEEE
14 years 11 months ago
2003
IEEE
In the previous work, the problem of nding gate delays to eliminate glitches has been solved by linear programs (LP) requiring an exponentially large number ofconstraints. By intr...
VLSID
2002
IEEE
14 years 11 months ago
2002
IEEE
Switching activity estimation is a crucial step in estimating dynamic power consumption in CMOS circuits. In [1], we proposed a new switching probability model based on Bayesian N...
ASPDAC
2006
ACM
14 years 5 months ago
2006
ACM
Abstract— Routing tree construction is a fundamental problem in modern VLSI design. In this paper we propose CDCTree, an Obstacle-Avoiding Rectilinear Steiner Minimum Tree (OARSM...
IH
1998
Springer
14 years 3 months ago
1998
Springer
Advanced CAD tools and high-density VLSI technologies have combined to create a new market for reusable digital designs. The economic viability of the new core-based design paradig...
EAAI
2007
13 years 11 months ago
2007
This paper presents a swarm intelligence based approach to optimally partition combinational CMOS circuits for pseudoexhaustive testing. The partitioning algorithm ensures reducti...