Simulated annealing based standard cell placement for VLSI designs has long been acknowledged as a compute-intensive process. All previous work in parallel simulated annealing bas...
State-of-the-art technologies in very large scale integration (VLSI) allow for the realization of gates with varying energy consumptions and hence delays (i.e., processing speeds) ...
— Excessive instantaneous power consumption may reduce the reliability and performance of VLSI chips. Hence, to synthesize circuits with high reliability, it is imperative to efï...
With scaling of CMOS technologies, sub-threshold, gate and reverse biased junction band-to-band-tunneling leakage have increased dramatically. Together they account for more than 2...
We propose a novel, non-simulative, probabilistic model for switching activity in sequential circuits, capturing both spatio-temporal correlations at internal nodes and higher ord...
Sanjukta Bhanja, Karthikeyan Lingasubramanian, N. ...