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» Verifying VLSI Circuits
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ICCD
1997
IEEE
123views Hardware» more  ICCD 1997»
14 years 3 months ago
A Parallel Circuit-Partitioned Algorithm for Timing Driven Cell Placement
Simulated annealing based standard cell placement for VLSI designs has long been acknowledged as a compute-intensive process. All previous work in parallel simulated annealing bas...
John A. Chandy, Prithviraj Banerjee
ARCS
2006
Springer
14 years 2 months ago
Biologically-Inspired Optimization of Circuit Performance and Leakage: A Comparative Study
State-of-the-art technologies in very large scale integration (VLSI) allow for the realization of gates with varying energy consumptions and hence delays (i.e., processing speeds) ...
Ralf Salomon, Frank Sill
TVLSI
1998
81views more  TVLSI 1998»
13 years 10 months ago
Maximum power estimation for CMOS circuits using deterministic and statistical approaches
— Excessive instantaneous power consumption may reduce the reliability and performance of VLSI chips. Hence, to synthesize circuits with high reliability, it is imperative to efï...
Chuan-Yu Wang, Kaushik Roy
VLSID
2007
IEEE
152views VLSI» more  VLSID 2007»
14 years 11 months ago
An Efficient Technique for Leakage Current Estimation in Sub 65nm Scaled CMOS Circuits Based on Loading Effect
With scaling of CMOS technologies, sub-threshold, gate and reverse biased junction band-to-band-tunneling leakage have increased dramatically. Together they account for more than 2...
Ashesh Rastogi, Wei Chen, Alodeep Sanyal, Sandip K...
VLSID
2005
IEEE
255views VLSI» more  VLSID 2005»
14 years 11 months ago
Estimation of Switching Activity in Sequential Circuits Using Dynamic Bayesian Networks
We propose a novel, non-simulative, probabilistic model for switching activity in sequential circuits, capturing both spatio-temporal correlations at internal nodes and higher ord...
Sanjukta Bhanja, Karthikeyan Lingasubramanian, N. ...