222 search results - page 10 / 45 » Verifying an Arbiter Circuit |
ISCAS
2003
IEEE
14 years 1 months ago
2003
IEEE
This paper presents a mathematical analysis of the ripple voltage caused by a mismatch in parasitic capacitances in multi-phase, clocked charge pumps. Through detailed circuit mod...
ASPDAC
2006
ACM
14 years 1 months ago
2006
ACM
— A new algorithm is proposed to reduce the number of intermediate registers of a pipelined circuit using a combination of multi-clock cycle paths and clock scheduling. The algor...
ISLPED
2006
ACM
14 years 1 months ago
2006
ACM
In this paper, we identify the key challenges that oppose subthreshold circuit design and describe fabricated chips that verify techniques for overcoming the challenges. Categorie...
ASPDAC
2001
ACM
13 years 11 months ago
2001
ACM
Abstract- Traditional state-traversal-basedmethods for verifying sequential circuits are computationally infeasible for circuits with a large number of memory elements. However, if...
CONCUR
1998
Springer
14 years 4 days ago
1998
Springer
In this paper we solve the following problem: \given a digital circuit composed of gates whose real-valued delays are in an integerbounded interval, is there a way to discretize ti...