222 search results - page 11 / 45 » Verifying an Arbiter Circuit |
ATVA
2007
Springer
13 years 12 months ago
2007
Springer
Abstract. Symbolic Trajectory Evaluation (STE) is a powerful technique for hardware model checking. It is based on a 3-valued symbolic simulation, using 0,1 and X n"), where t...
ASYNC
2002
IEEE
14 years 27 days ago
2002
IEEE
Wire and gate delays are accounted to have equal, or nearly equal, effect on circuit behavior in modern design techniques. This paper introduces a new approach to verify circuits ...
ISPD
2000
ACM
14 years 8 days ago
2000
ACM
We propose a gate resizing method for delay and power optimization that is based on statistical static timing analysis. Our method focuses on the component of timing uncertainties...
ICALP
2010
Springer
13 years 5 months ago
2010
Springer
Abstract. We present a method for verifying measurement-based quantum computations, by producing a quantum circuit equivalent to a given deterministic measurement pattern. We defin...
GLVLSI
2007
IEEE
14 years 2 months ago
2007
IEEE
Threshold logic is gaining prominence as an alternative to Boolean logic. The main reason for this trend is the availability of devices that implement these circuits efficiently (...