222 search results - page 17 / 45 » Verifying an Arbiter Circuit |
DAC
2004
ACM
14 years 9 months ago
2004
ACM
Current Static Timing Analysis (STA) techniques allow one to verify the timing of a circuit at different process corners which only consider cases where all the supplies are low o...
HOST
2009
IEEE
14 years 2 months ago
2009
IEEE
Abstract—Rapid advances in integrated circuit (IC) development predicted by Moore’s Law lead to increasingly complex, hard to verify IC designs. Design insiders or adversaries ...
ASYNC
2002
IEEE
14 years 27 days ago
2002
IEEE
Advanced clock-delayed1 and self-resetting domino circuits are becoming increasingly important design styles in aggressive synchronous as well as asynchronous design. Their design...
GLVLSI
2006
IEEE
14 years 2 months ago
2006
IEEE
A new circuit technique based on a single PMOS sleep transistor and a dual threshold voltage CMOS technology is proposed in this paper for simultaneously reducing subthreshold and...
DAC
1999
ACM
14 years 9 months ago
1999
ACM
We propose a method for power optimization that considers glitch reduction by gate sizing based on the statistical estimation of glitch transitions. Our method reduces not only th...