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» Verifying an Arbiter Circuit
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ICCAD
2008
IEEE
98views Hardware» more  ICCAD 2008»
14 years 4 months ago
Scalable and scalably-verifiable sequential synthesis
This paper describes an efficient implementation of an effective sequential synthesis operation that uses induction to detect and merge sequentially-equivalent nodes. State-encodi...
Alan Mishchenko, Michael L. Case, Robert K. Brayto...
ICCAD
2006
IEEE
131views Hardware» more  ICCAD 2006»
14 years 4 months ago
Fast wire length estimation by net bundling for block placement
The wire length estimation is the bottleneck of packing based block placers. To cope with this problem, we present a fast wire length estimation method in this paper. The key idea...
Tan Yan, Hiroshi Murata
DAC
2009
ACM
14 years 2 months ago
Information hiding for trusted system design
For a computing system to be trusted, it is equally important to verify that the system performs no more and no less functionalities than desired. Traditional testing and verifica...
Junjun Gu, Gang Qu, Qiang Zhou
DATE
2009
IEEE
167views Hardware» more  DATE 2009»
14 years 2 months ago
Analyzing the impact of process variations on parametric measurements: Novel models and applications
Abstract—In this paper we propose a novel statistical framework to model the impact of process variations on semiconductor circuits through the use of process sensitive test stru...
Sherief Reda, Sani R. Nassif
ISCAS
2007
IEEE
103views Hardware» more  ISCAS 2007»
14 years 2 months ago
A Low-cost and High-performance SoC Design for OMA DRM2 Applications
A SoC design for applications of OMA DRM 2 Agent in mobile phones is presented in this paper, which has been verified by Altera Stratix EP1S80B956C6 FPGA development board. Several...
Yehua Gu, Xiaoyang Zeng, Jun Han, Jia Zhao