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» Verifying an Arbiter Circuit
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FPGA
2003
ACM
161views FPGA» more  FPGA 2003»
14 years 1 months ago
Implementation of BEE: a real-time large-scale hardware emulation engine
This paper describes the hardware implementation of a real-time, large-scale, multi-chip FPGA (Field Programmable Gate Array) based emulation engine with a capacity of 10 million ...
Chen Chang, Kimmo Kuusilinna, Brian C. Richards, R...
DATE
2010
IEEE
134views Hardware» more  DATE 2010»
14 years 1 months ago
Pseudo-CMOS: A novel design style for flexible electronics
Flexible electronics have attracted much attention since they enable promising applications such as lowcost RFID tags and e-paper. Thin-film transistors (TFTs) are considered as ...
Tsung-Ching Huang, Kenjiro Fukuda, Chun-Ming Lo, Y...
GLVLSI
2002
IEEE
95views VLSI» more  GLVLSI 2002»
14 years 29 days ago
Term ordering problem on MDG
As an efficient representation of Extended Finite State Machines, Multiway Decision Graphs (MDG) are suitable for automatic hardware verification of Register Transfer Level (RTL) ...
Yi Feng, Eduard Cerny
ISLPED
2000
ACM
70views Hardware» more  ISLPED 2000»
14 years 11 days ago
An adaptive on-chip voltage regulation technique for low-power applications
In this paper we present a completely on-chip voltage regulation technique which promises to adjust the degree of voltage regulation in a digital logic chip in the face of process...
Nicola Dragone, Akshay Aggarwal, L. Richard Carley
TABLEAUX
1998
Springer
14 years 6 days ago
Model Checking: Historical Perspective and Example (Extended Abstract)
ple (Extended Abstract) Edmund M. Clarke and Sergey Berezin Carnegie Mellon University -- USA Model checking is an automatic verification technique for finite state concurrent syst...
Edmund M. Clarke, Sergey Berezin