222 search results - page 7 / 45 » Verifying an Arbiter Circuit |
ISCAS
2002
IEEE
2002
IEEE
Latchup current self-stop circuit for whole-chip latchup prevention in bulk CMOS integrated circuits
14 years 25 days ago
A latchup current self-stop methodology and circuit design, which are used to prevent damage in the bulk CMOS integrated circuits due to latchup, are proposed in this paper. In a ...
NN
2008
Springer
13 years 7 months ago
2008
Springer
A silicon neuron circuit that produces spiking and bursting firing patterns, with biologically plausible spike shape, is presented. The circuit mimics the behaviour of known class...
ASYNC
2002
IEEE
14 years 26 days ago
2002
IEEE
We present a method for synchronizing pausible clocks in GALS (Globally Asynchronous, Locally Synchronous) systems. In contrast to most conventional GALS schemes the method is not...
ICCAD
1996
IEEE
14 years 2 days ago
1996
IEEE
This paper presents a new framework for formal logic verification. What is depicted here is fundamentally different from previous approaches. In earlier approaches, the circuit is ...
DAC
2005
ACM
14 years 8 months ago
2005
ACM
el Predicate Abstraction and Refinement for Verifying RTL Verilog Himanshu Jain CMU SCS, Pittsburgh, PA 15213 Daniel Kroening ETH Z?urich, Switzerland Natasha Sharygina CMU SCS an...