Sciweavers

357 search results - page 40 / 72
» Verifying properties of process definitions
Sort
View
ATVA
2006
Springer
131views Hardware» more  ATVA 2006»
15 years 6 months ago
Timed Unfoldings for Networks of Timed Automata
Whereas partial order methods have proved their efficiency for the analysis of discrete-event systems, their application to timed systems remains a challenging research topic. Here...
Patricia Bouyer, Serge Haddad, Pierre-Alain Reynie...
ASYNC
2007
IEEE
129views Hardware» more  ASYNC 2007»
15 years 7 months ago
Formal Verification of CHP Specifications with CADP Illustration on an Asynchronous Network-on-Chip
Few formal verification techniques are currently available for asynchronous designs. In this paper, we describe a new approach for the formal verification of asynchronous architec...
Gwen Salaün, Wendelin Serwe, Yvain Thonnart, ...
ASE
2008
102views more  ASE 2008»
15 years 3 months ago
Model driven code checking
Model checkers were originally developed to support the formal verification of high-level design models of distributed system designs. Over the years, they have become unmatched in...
Gerard J. Holzmann, Rajeev Joshi, Alex Groce
FASE
2009
Springer
15 years 7 months ago
Certification of Smart-Card Applications in Common Criteria
This paper describes the certification of smart-card applications in the framework of Common Criteria. In this framework, a smart-card application is represented by a model of its...
Iman Narasamdya, Michaël Périn
ENTCS
2006
112views more  ENTCS 2006»
15 years 3 months ago
Modeling Web Applications by the Multiple Levels of Integrity Policy
We propose a formal method to validate the reliability of a web application, by modeling interactions among its constituent objects. Modeling exploits the recent "Multiple Le...
Gianluca Amato, Massimo Coppola, Stefania Gnesi, F...