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» Versatile Processor Design for Efficiency and High Performan...
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112
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VLSID
2005
IEEE
87views VLSI» more  VLSID 2005»
16 years 4 months ago
Synthesis of Asynchronous Circuits Using Early Data Validity
Interest in asynchronous circuit design is increasing due to its promise of efficient designs. The quiescent nature of asynchronous circuits allows them to remain in a stable stat...
Nitin Gupta, Doug A. Edwards
122
Voted
MICRO
2009
IEEE
99views Hardware» more  MICRO 2009»
15 years 10 months ago
Low-cost router microarchitecture for on-chip networks
On-chip networks are critical to the scaling of future multicore processors. The challenge for on-chip network is to reduce the cost including power consumption and area while pro...
John Kim
142
Voted
IPPS
2008
IEEE
15 years 10 months ago
A plug-and-play model for evaluating wavefront computations on parallel architectures
This paper develops a plug-and-play reusable LogGP model that can be used to predict the runtime and scaling behavior of different MPI-based pipelined wavefront applications runni...
Gihan R. Mudalige, Mary K. Vernon, Stephen A. Jarv...
156
Voted
LCTRTS
2007
Springer
15 years 9 months ago
Compiler-managed partitioned data caches for low power
Set-associative caches are traditionally managed using hardwarebased lookup and replacement schemes that have high energy overheads. Ideally, the caching strategy should be tailor...
Rajiv A. Ravindran, Michael L. Chu, Scott A. Mahlk...
139
Voted
MICRO
2008
IEEE
103views Hardware» more  MICRO 2008»
15 years 10 months ago
Testudo: Heavyweight security analysis via statistical sampling
Heavyweight security analysis systems, such as taint analysis and dynamic type checking, are powerful technologies used to detect security vulnerabilities and software bugs. Tradi...
Joseph L. Greathouse, Ilya Wagner, David A. Ramos,...