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MICRO
2010
IEEE
140views Hardware» more  MICRO 2010»
13 years 6 months ago
STEM: Spatiotemporal Management of Capacity for Intra-core Last Level Caches
Efficient management of last level caches (LLCs) plays an important role in bridging the performance gap between processor cores and main memory. This paper is motivated by two key...
Dongyuan Zhan, Hong Jiang, Sharad C. Seth
BIRTHDAY
2003
Springer
14 years 2 months ago
Spatial Data Management for Virtual Product Development
Abstract: In the automotive and aerospace industry, millions of technical documents are generated during the development of complex engineering products. Particularly, the universa...
Hans-Peter Kriegel, Martin Pfeifle, Marco Pöt...
DAC
2008
ACM
14 years 10 months ago
DVFS in loop accelerators using BLADES
Hardware accelerators are common in embedded systems that have high performance requirements but must still operate within stringent energy constraints. To facilitate short time-t...
Ganesh S. Dasika, Shidhartha Das, Kevin Fan, Scott...
ISJGP
2007
146views more  ISJGP 2007»
13 years 8 months ago
End-to-End Security Across Wired-Wireless Networks for Mobile Users
Abstract  Recent advances in mobile computing and wireless communication technologies are enabling high mobility and flexibility of anytime, anywhere service access for mobile us...
Sherali Zeadally, Nicolas Sklavos, Moganakrishnan ...
ICCAD
2010
IEEE
141views Hardware» more  ICCAD 2010»
13 years 6 months ago
Local clock skew minimization using blockage-aware mixed tree-mesh clock network
Clock network construction is one key problem in high performance VLSI design. Reducing the clock skew variation is one of the most important objectives during clock network synthe...
Linfu Xiao, Zigang Xiao, Zaichen Qian, Yan Jiang, ...