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AICCSA
2007
IEEE
99views Hardware» more  AICCSA 2007»
14 years 23 days ago
An Efficient Processor Allocation Strategy that Maintains a High Degree of Contiguity among Processors in 2D Mesh Connected Mult
Two strategies are used for the allocation of jobs to processors connected by mesh topologies: contiguous allocation and non-contiguous allocation. In noncontiguous allocation, a ...
Saad Bani-Mohammad, Mohamed Ould-Khaoua, Ismail Ab...
ICMENS
2005
IEEE
98views Hardware» more  ICMENS 2005»
14 years 2 months ago
Versatile Inertial Displacement Sensor for Planar Motion
Inertial displacement sensors employing currently available high performance micromachined accelerometers and gyroscopes measure position and attitude with sub-micron accuracy for ...
Swavik A. Spiewak
ITC
1998
IEEE
95views Hardware» more  ITC 1998»
14 years 1 months ago
Native mode functional test generation for processors with applications to self test and design validation
New methodologies based on functional testing and built-in self-test can narrow the gap between necessary solutions and existing techniques for processor validation and testing. W...
Jian Shen, Jacob A. Abraham
CODES
2006
IEEE
14 years 2 months ago
A bus architecture for crosstalk elimination in high performance processor design
In deep sub-micron technology, the crosstalk effect between adjacent wires has become an important issue, especially between long on-chip buses. This effect leads to the increas...
Wen-Wen Hsieh, Po-Yuan Chen, TingTing Hwang
ICCD
2001
IEEE
120views Hardware» more  ICCD 2001»
14 years 5 months ago
Design of a Predictive Filter Cache for Energy Savings in High Performance Processor Architectures
Filter cache has been proposed as an energy saving architectural feature [9]. A filter cache is placed between the CPU and the instruction cache (I-cache) to provide the instruct...
Weiyu Tang, Rajesh K. Gupta, Alexandru Nicolau