138 search results - page 9 / 28 » Very Compact FPGA Implementation of the AES Algorithm |
GLVLSI
2007
IEEE
13 years 11 months ago
2007
IEEE
This paper presents a pipelined architecture of a modular Montgomery multiplier, which is suitable to be used in public key coprocessors. Starting from a baseline implementation o...
CHES
2007
Springer
14 years 1 months ago
2007
Springer
This paper describes a modular exponentiation processing method and circuit architecture that can exhibit the maximum performance of FPGA resources. The modular exponentiation arch...
DAC
1995
ACM
13 years 11 months ago
1995
ACM
—In this paper, we present an algorithm for finding a good Ashenhurst decomposition of a switching function. Most current methods for performing this type of decomposition are ba...
ICC
2011
IEEE
12 years 7 months ago
2011
IEEE
—Regular expression matching has become a critical yet challenging technique in content-aware network processing, such as application identification and deep inspection. To meet ...
FPGA
2003
ACM
14 years 19 days ago
2003
ACM
In this paper, we present the first exact algorithm to solve the constrained I/O placement problem for FPGAs that support multiple I/O standards. We derive a compact integer line...