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RT
2001
Springer
14 years 29 days ago
A Perceptually-Based Texture Caching Algorithm for Hardware-Based Rendering
: The performance of hardware-based interactive rendering systems is often constrained by polygon fill rates and texture map capacity, rather than polygon count alone. We present a...
Reynald Dumont, Fabio Pellacini, James A. Ferwerda
CASES
2007
ACM
14 years 16 days ago
Eliminating inter-process cache interference through cache reconfigurability for real-time and low-power embedded multi-tasking
We propose a technique which leverages configurable data caches to address the problem of cache interference in multitasking embedded systems. Data caches are often necessary to p...
Rakesh Reddy, Peter Petrov
SC
1995
ACM
14 years 2 days ago
Architectural Mechanisms for Explicit Communication in Shared Memory Multiprocessors
The goal of this work is to explore architectural mechanisms for supporting explicit communication in cachecoherent shared memory multiprocessors. The motivation stems from the ob...
Umakishore Ramachandran, Gautam Shah, Anand Sivasu...
FTDCS
2003
IEEE
14 years 1 months ago
Distributed Shared State
Increasingly, Internet-level distributed systems are oriented as much toward information access as they are toward computation. From computer-supported collaborative work to peer-...
Michael L. Scott, DeQing Chen, Sandhya Dwarkadas, ...
ICS
2009
Tsinghua U.
14 years 1 months ago
Dynamic task set partitioning based on balancing memory requirements to reduce power consumption
ABSTRACT Because of technology advances power consumption has emerged up as an important design issue in modern high-performance microprocessors. As a consequence, research on redu...
Diana Bautista, Julio Sahuquillo, Houcine Hassan, ...