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ISQED
2008
IEEE
150views Hardware» more  ISQED 2008»
14 years 2 months ago
Dominant Substrate Noise Coupling Mechanism for Multiple Switching Gates
— The dominant substrate noise coupling mechanism is determined for multiple switching gates based on a physically intuitive model. The model exhibits reasonable accuracy as comp...
Emre Salman, Eby G. Friedman, Radu M. Secareanu, O...
DATE
1998
IEEE
76views Hardware» more  DATE 1998»
13 years 12 months ago
Gated Clock Routing Minimizing the Switched Capacitance
This paper presents a zero-skew gated clock routing technique for VLSI circuits. The gated clock tree has masking gates at the internal nodes of the clock tree, which are selectiv...
Jaewon Oh, Massoud Pedram
GLVLSI
2003
IEEE
146views VLSI» more  GLVLSI 2003»
14 years 29 days ago
A practical CAD technique for reducing power/ground noise in DSM circuits
One of the fundamental problems in Deep Sub Micron (DSM) circuits is Simultaneous Switching Noise (SSN), which causes voltage fluctuations in the circuit power/ground networks. In...
Arindam Mukherjee, Krishna Reddy Dusety, Rajsaktis...
JSAC
2007
95views more  JSAC 2007»
13 years 7 months ago
Experiences in implementing an experimental wide-area GMPLS network
In this article, we describe our experiences in implementing an experimental wide-area GMPLS network called CHEETAH (Circuit-Switched End-to-End Transport Architecture). The key c...
Xiangfei Zhu, Xuan Zheng, Malathi Veeraraghavan
DATE
2005
IEEE
116views Hardware» more  DATE 2005»
14 years 1 months ago
Uniformly-Switching Logic for Cryptographic Hardware
Recent work on Differential Power Analysis shows that even mathematically-secure cryptographic protocols may be vulnerable at the physical implementation level. By measuring energ...
Igor L. Markov, Dmitri Maslov