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ICCAD
2010
IEEE
125views Hardware» more  ICCAD 2010»
13 years 5 months ago
Peak current reduction by simultaneous state replication and re-encoding
Reducing circuit's peak current plays an important role in circuit reliability in deep sub-micron era. For sequential circuits, it is observed that the peak current has a str...
Junjun Gu, Gang Qu, Lin Yuan, Qiang Zhou
ASPDAC
2008
ACM
104views Hardware» more  ASPDAC 2008»
13 years 9 months ago
Low power clock buffer planning methodology in F-D placement for large scale circuit design
Traditionally, clock network layout is performed after cell placement. Such methodology is facing a serious problem in nanometer IC designs where people tend to use huge clock buff...
Yanfeng Wang, Qiang Zhou, Yici Cai, Jiang Hu, Xian...
FCCM
2006
IEEE
131views VLSI» more  FCCM 2006»
14 years 1 months ago
Packet Switched vs. Time Multiplexed FPGA Overlay Networks
— Dedicated, spatially configured FPGA interconnect is efficient for applications that require high throughput connections between processing elements (PEs) but with a limited ...
Nachiket Kapre, Nikil Mehta, Michael DeLorimier, R...
ISMVL
2003
IEEE
83views Hardware» more  ISMVL 2003»
14 years 1 months ago
Multiple-Valued Dynamic Source-Coupled Logic
A new multiple-valued current-mode (MVCM) integrated circuit based on dynamic source-coupled logic (SCL) is proposed for low-power VLSI applications. The use of a precharge-evalua...
Takahiro Hanyu, Akira Mochizuki, Michitaka Kameyam...
HOTNETS
2010
13 years 2 months ago
Proteus: a topology malleable data center network
Full-bandwidth connectivity between all servers of a data center may be necessary for all-to-all traffic patterns, but such interconnects suffer from high cost, complexity, and en...
Ankit Singla, Atul Singh, Kishore Ramachandran, Le...