In this paper, we propose a timing dependent dynamic power estimation framework that considers the impact of coupling and glitches. We show that relative switching activities and ...
Debjit Sinha, DiaaEldin Khalil, Yehea I. Ismail, H...
Abstract—Power/ground noise is a major source of VLSI circuit timing variations. This work aims to reduce clock network induced power noise by assigning different signal polariti...
This paper presents the design and experimental results of fully integrated CMOS power sensors for RF built-in self-test (BIST) applications. Using a standard 0.18- m CMOS process...
- The problem of determining lower bounds for the energy cost of a given nanoscale design is addressed via a complexity theory-based approach. This paper provides a theoretical fra...
Abstract— This paper describes the fast-scale bifurcation phenomena of a single-stage power-factor-correction (PFC) power supply which is commonly used in low power applications....
Xiaoqun Wu, Chi Kong Tse, Octavian Dranga, Junan L...