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SIGGRAPH
1994
ACM
14 years 1 months ago
Priority rendering with a virtual reality address recalculation pipeline
Virtual reality systems are placing never before seen demands on computer graphics hardware, yet few graphics systems are designed specifically for virtual reality. An address rec...
Matthew Regan, Ronald Pose
TVLSI
2008
169views more  TVLSI 2008»
13 years 9 months ago
Energy-Aware Flash Memory Management in Virtual Memory System
The traditional virtual memory system is designed for decades assuming a magnetic disk as the secondary storage. Recently, flash memory becomes a popular storage alternative for ma...
Han-Lin Li, Chia-Lin Yang, Hung-Wei Tseng
ISCA
2010
IEEE
205views Hardware» more  ISCA 2010»
14 years 2 months ago
The virtual write queue: coordinating DRAM and last-level cache policies
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
Jeffrey Stuecheli, Dimitris Kaseridis, David Daly,...
ISCA
2007
IEEE
111views Hardware» more  ISCA 2007»
14 years 4 months ago
Express virtual channels: towards the ideal interconnection fabric
Due to wire delay scalability and bandwidth limitations inherent in shared buses and dedicated links, packet-switched on-chip interconnection networks are fast emerging as the per...
Amit Kumar 0002, Li-Shiuan Peh, Partha Kundu, Nira...
WSC
1998
13 years 11 months ago
Communication Mission-type Orders to Virtual Commanders
This paper discusses issues in modeling C4I and cognitive processes in next generation simulations and applications to Force XXI command and control. We propose a modification to ...
Martin S. Kleiner, Scott A. Carey, Joseph E. Beach