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RTAS
2005
IEEE
14 years 2 months ago
Bounding Worst-Case Data Cache Behavior by Analytically Deriving Cache Reference Patterns
While caches have become invaluable for higher-end architectures due to their ability to hide, in part, the gap between processor speed and memory access times, caches (and partic...
Harini Ramaprasad, Frank Mueller
DATE
2002
IEEE
166views Hardware» more  DATE 2002»
14 years 1 months ago
Event Model Interfaces for Heterogeneous System Analysis
Complex embedded systems consist of hardware and software components from different domains, such as control and signal processing, many of them supplied by different IP vendors. ...
Kai Richter, Rolf Ernst
GECON
2008
Springer
152views Business» more  GECON 2008»
13 years 9 months ago
The Power of Preemption in Economic Online Markets
Abstract. In distributed computer networks where resources are under decentralized control, selfish users will generally not work towards one common goal, such as maximizing the o...
Lior Amar, Ahuva Mu'alem, Jochen Stößer
RTSS
1999
IEEE
14 years 26 days ago
Timing Anomalies in Dynamically Scheduled Microprocessors
Previous timing analysis methods have assumed that the worst-case instruction execution time necessarily corresponds to the worst-case behavior. We show that this assumption is wr...
Thomas Lundqvist, Per Stenström
RTSS
2000
IEEE
14 years 29 days ago
Scalable Real-Time System Design using Preemption Thresholds
The maturity of schedulabilty analysis techniquesfor fired-prioritypreemptive scheduling has enabled the consideration of timing issues at design time using a specification of the...
Manas Saksena, Yun Wang