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DAC
2003
ACM
14 years 8 months ago
Performance-impact limited area fill synthesis
Chemical-mechanical planarization (CMP) and other manufacturing steps in very deep-submicron VLSI have varying effects on device and interconnect features, depending on the local ...
Yu Chen, Puneet Gupta, Andrew B. Kahng
VLSID
2002
IEEE
98views VLSI» more  VLSID 2002»
14 years 8 months ago
On Test Scheduling for Core-Based SOCs
We present a mathematical model for the problem of scheduling tests for core-based system-on-chip (SOC) VLSI designs. Given a set of tests for each core in the SOC and a set of te...
Sandeep Koranne
IPPS
2007
IEEE
14 years 1 months ago
Strategies for Replica Placement in Tree Networks
In this paper, we discuss and compare several policies to place replicas in tree networks, subject to server capacity constraints. The client requests are known beforehand, while ...
Anne Benoit, Veronika Rehn, Yves Robert
MSN
2007
Springer
125views Sensor Networks» more  MSN 2007»
14 years 1 months ago
Ensuring Area Coverage in Hybrid Wireless Sensor Networks
Success of Wireless Sensor Networks largely depends whether the deployed network can provide desired coverage with acceptable network lifetime. This paper proposes a distributed pr...
Nadeem Ahmed, Salil S. Kanhere, Sanjay Jha
ASPDAC
2006
ACM
134views Hardware» more  ASPDAC 2006»
14 years 1 months ago
Constraint driven I/O planning and placement for chip-package co-design
System-on-chip and system-in-package result in increased number of I/O cells and complicated constraints for both chip designs and package designs. This renders the traditional ma...
Jinjun Xiong, Yiu-Chung Wong, Egino Sarto, Lei He