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ISLPED
2005
ACM
87views Hardware» more  ISLPED 2005»
14 years 2 months ago
Runtime identification of microprocessor energy saving opportunities
High power consumption and low energy efficiency have become significant impediments to future performance improvements in modern microprocessors. This paper contributes to the so...
W. L. Bircher, M. Valluri, J. Law, L. K. John
HPCA
2005
IEEE
14 years 2 months ago
Microarchitectural Wire Management for Performance and Power in Partitioned Architectures
Future high-performance billion-transistor processors are likely to employ partitioned architectures to achieve high clock speeds, high parallelism, low design complexity, and low...
Rajeev Balasubramonian, Naveen Muralimanohar, Kart...
HPCA
2009
IEEE
14 years 9 months ago
A novel architecture of the 3D stacked MRAM L2 cache for CMPs
Magnetic Random Access Memory (MRAM) is considered to be a promising future memory technology due to its low leakage power, high density and fast read speed. The heterogeneous int...
Guangyu Sun, Xiangyu Dong, Yuan Xie, Jian Li, Yira...
NOCS
2009
IEEE
14 years 3 months ago
Best of both worlds: A bus enhanced NoC (BENoC)
While NoCs are efficient in delivering high throughput point-to-point traffic, their multi-hop operation is too slow for latency sensitive signals. In addition, NoCS are inefficie...
Ran Manevich, Isask'har Walter, Israel Cidon, Avin...
VLSID
2008
IEEE
138views VLSI» more  VLSID 2008»
14 years 9 months ago
Memory Architecture Exploration Framework for Cache Based Embedded SOC
Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and l...
T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindaraj...