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DAC
2006
ACM
14 years 1 months ago
A reconfigurable design-for-debug infrastructure for SoCs
In this paper we present a Design-for-Debug (DFD) reconfigurable infrastructure for SoCs to support at-speed in-system functional debug. A distributed reconfigurable fabric insert...
Miron Abramovici, Paul Bradley, Kumar N. Dwarakana...
ISPAN
2005
IEEE
14 years 1 months ago
A Fast Noniterative Scheduler for Input-Queued Switches with Unbuffered Crossbars
Most high-end switches use an input-queued or a combined input- and output-queued architecture. The switch fabrics of these architectures commonly use an iterative scheduling syst...
Kevin F. Chen, Edwin Hsing-Mean Sha, S. Q. Zheng
FPL
2005
Springer
89views Hardware» more  FPL 2005»
14 years 1 months ago
Automatic Creation of Domain-Specific Reconfigurable CPLDs for SoC
Many System-on-a-Chip devices would benefit from the inclusion of reprogrammable logic on the silicon die, as it can add general computing ability, provide run-time reconfigurabil...
Mark Holland, Scott Hauck
GLVLSI
2007
IEEE
153views VLSI» more  GLVLSI 2007»
13 years 9 months ago
Address generation for nanowire decoders
Nanoscale crossbars built from nanowires can form high density memories and programmable logic devices. To integrate such nanoscale devices with other circuits, nanowire decoders ...
Jia Wang, Ming-Yang Kao, Hai Zhou
SI3D
2006
ACM
14 years 1 months ago
Relief mapping of non-height-field surface details
The ability to represent non-height-field mesostructure details is of great importance for rendering complex surface patterns, such as weave and multilayer structures. Currently,...
Fabio Policarpo, Manuel Menezes de Oliveira Neto