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» Web-Based Feature Reduction System: A Case Study
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ASAP
2005
IEEE
182views Hardware» more  ASAP 2005»
14 years 4 months ago
A Thread and Data-Parallel MPEG-4 Video Encoder for a System-On-Chip Multiprocessor
We studied the dynamic instruction count reduction for a single-thread, vectorized and a multi-threaded, non-vectorized, MPEG-4 video encoder. Results indicate a maximum improveme...
Tom R. Jacobs, José L. Núñez-...
CAV
2007
Springer
227views Hardware» more  CAV 2007»
14 years 2 months ago
The TASM Toolset: Specification, Simulation, and Formal Verification of Real-Time Systems
Abstract. In this paper, we describe the features of the Timed Abstract State Machine toolset. The toolset implements the features of the Timed Abstract State Machine (TASM) langua...
Martin Ouimet, Kristina Lundqvist
CSMR
2005
IEEE
14 years 4 months ago
Correlating Features and Code Using a Compact Two-Sided Trace Analysis Approach
Software developers are constantly required to modify and adapt application features in response to changing requirements. The problem is that just by reading the source code, it ...
Orla Greevy, Stéphane Ducasse
ICDCSW
2003
IEEE
14 years 3 months ago
Studying the Use of Handhelds to Control Smart Appliances
Abstract— Today’s complex appliances are plagued by difficultto-use interfaces. In many cases, consumers use only a few of the many features on their appliances because the mor...
Jeffrey Nichols, Brad A. Myers
ISSS
1995
IEEE
100views Hardware» more  ISSS 1995»
14 years 1 months ago
Power analysis and low-power scheduling techniques for embedded DSP software
This paper describes the application of a measurement based power analysis technique for an embedded DSP processor. An instruction-level power model for the processor has been dev...
Mike Tien-Chien Lee, Vivek Tiwari, Sharad Malik, M...