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GLVLSI
2009
IEEE
123views VLSI» more  GLVLSI 2009»
14 years 4 months ago
Power efficient tree-based crosslinks for skew reduction
Clock distribution networks are an important design issue that is highly dependent on delay variations and load imbalances, while requiring power efficiency. Existing mesh solutio...
Inna Vaisband, Ran Ginosar, Avinoam Kolodny, Eby G...
GLVLSI
2006
IEEE
113views VLSI» more  GLVLSI 2006»
14 years 3 months ago
Statistical gate delay calculation with crosstalk alignment consideration
We study gate delay variation caused by crosstalk aggressor alignment, i.e., difference of signal arrival times in coupled neighboring interconnects. This effect is as significan...
Andrew B. Kahng, Bao Liu, Xu Xu
GLVLSI
2006
IEEE
155views VLSI» more  GLVLSI 2006»
14 years 3 months ago
Dynamic voltage scaling for multitasking real-time systems with uncertain execution time
Dynamic voltage scaling (DVS) for real-time systems has been extensively studied to save energy. Previous studies consider the probabilistic distributions of tasks’ execution ti...
Changjiu Xian, Yung-Hsiang Lu
ASPDAC
2010
ACM
161views Hardware» more  ASPDAC 2010»
13 years 7 months ago
A dual-MST approach for clock network synthesis
Abstract--In nanometer-scale VLSI physical design, clock network becomes a major concern on determining the total performance of digital circuit. Clock skew and PVT (Process, Volta...
Jingwei Lu, Wing-Kai Chow, Chiu-Wing Sham, Evangel...
GLVLSI
2005
IEEE
110views VLSI» more  GLVLSI 2005»
14 years 3 months ago
QCA channel routing with wire crossing minimization
Quantum-dot Cellular Automata (QCA) is a novel computing mechanism that can represent binary information based on spatial distribution of electron charge configuration in chemica...
Brian Stephen Smith, Sung Kyu Lim