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DATE
2006
IEEE
114views Hardware» more  DATE 2006»
14 years 5 months ago
An efficient static algorithm for computing the soft error rates of combinational circuits
Soft errors have emerged as an important reliability challenge for nanoscale VLSI designs. In this paper, we present a fast and efficient soft error rate (SER) computation algorit...
Rajeev R. Rao, Kaviraj Chopra, David Blaauw, Denni...
ASPDAC
2006
ACM
143views Hardware» more  ASPDAC 2006»
14 years 5 months ago
CDCTree: novel obstacle-avoiding routing tree construction based on current driven circuit model
Abstract— Routing tree construction is a fundamental problem in modern VLSI design. In this paper we propose CDCTree, an Obstacle-Avoiding Rectilinear Steiner Minimum Tree (OARSM...
Yiyu Shi, Tong Jing, Lei He, Zhe Feng 0002, Xianlo...
DFT
2005
IEEE
178views VLSI» more  DFT 2005»
14 years 4 months ago
Inter-Plane Via Defect Detection Using the Sensor Plane in 3-D Heterogeneous Sensor Systems
Defect and fault tolerance is being studied in a 3D Heterogeneous Sensor using a stacked chip with sensors located on the top plane, and inter-plane vias connecting these to other...
Glenn H. Chapman, Vijay K. Jain, Shekhar Bhansali
ISCAS
1999
IEEE
106views Hardware» more  ISCAS 1999»
14 years 3 months ago
Repeater insertion in RLC lines for minimum propagation delay
- A closed form expression for the propagation delay of a CMOS gate driving a distributed RLC line is introduced that is within 5% of dynamic circuit simulations for a wide range o...
Yehea I. Ismail, Eby G. Friedman
PC
2007
112views Management» more  PC 2007»
13 years 10 months ago
Service address routing: a network-embedded resource management layer for cluster computing
Service address routing is introduced as a novel and powerful paradigm for the integration of resource management functions into the interconnection fabric of cluster computers. S...
Isaac D. Scherson, Daniel S. Valencia, Enrique Cau...