Clock mesh is popular in high performance VLSI design because it is more robust against variations than clock tree at a cost of higher power consumption. In this paper, we propose ...
Tools and a design methodology have been developed to support partial run-time reconfiguration of FPGA logic on the Field Programmable Port Extender. High-speed Internet packet pr...
Edson L. Horta, John W. Lockwood, David E. Taylor,...
Designing and planning of the switching, signaling and support network is a fairly complex process in cellular mobile network. In this paper, the problem of assigning cells to swi...
Three-dimensional integrated circuits (3D ICs) offer a promising solution to overcome the on-chip communication bottleneck and improve performance over traditional two-dimensional...
With shrinking feature size and growing integration density in the Deep Sub-Micron technologies, the global buses are fast becoming the “weakest-links” in VLSI design. They ha...