2212 search results - page 427 / 443 » Weighted control scheduling |
HPCA
2005
IEEE
14 years 9 months ago
2005
IEEE
ZettaRAMTM is a new memory technology under development by ZettaCoreTM as a potential replacement for conventional DRAM. The key innovation is replacing the conventional capacitor...
ICCAD
2006
IEEE
14 years 5 months ago
2006
IEEE
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
CSCW
2010
ACM
14 years 5 months ago
2010
ACM
People are often required to catch up on information they have missed in meetings, because of lateness or scheduling conflicts. Catching up is a complex cognitive process where pe...
DSD
2009
IEEE
14 years 3 months ago
2009
IEEE
Abstract—Verification of application requirements is becoming a bottleneck in system-on-chip design, as the number of applications grows. Traditionally, the verification comple...
RTSS
2009
IEEE
14 years 3 months ago
2009
IEEE
—Emerging applications of wireless sensor networks (WSNs) require real-time quality of service (QoS) guarantees to be provided by the network. However, designing real-time schedu...