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DAC
2006
ACM
14 years 12 months ago
Statistical logic cell delay analysis using a current-based model
A statistical model for the purpose of logic cell timing analysis in the presence of process variations is presented. A new current-based cell delay model is utilized, which can a...
Hanif Fatemi, Shahin Nazarian, Massoud Pedram
DAGSTUHL
1996
14 years 6 days ago
What Not to Do When Writing an Interpreter for Specialisation
A partial evaluator, given a program and a known "static" part of its input data, outputs a specialised or residual program in which computations depending only on the st...
Neil D. Jones
ICCAD
2009
IEEE
119views Hardware» more  ICCAD 2009»
13 years 8 months ago
Iterative layering: Optimizing arithmetic circuits by structuring the information flow
Current logic synthesis techniques are ineffective for arithmetic circuits. They perform poorly for XOR-dominated circuits, and those with a high fan-in dependency between inputs ...
Ajay K. Verma, Philip Brisk, Paolo Ienne
AMAST
2000
Springer
14 years 3 months ago
Step by Step to Histories
The behavior of reactive systems is typically speci ed by state machines. This results in an operational description of how a system its output. An alternative and more abstract ap...
Max Breitling, Jan Philipps
MFCS
2009
Springer
14 years 5 months ago
Size and Energy of Threshold Circuits Computing Mod Functions
Let C be a threshold logic circuit computing a Boolean function MODm : {0, 1}n → {0, 1}, where n ≥ 1 and m ≥ 2. Then C outputs “0” if the number of “1”s in an input ...
Kei Uchizawa, Takao Nishizeki, Eiji Takimoto