A statistical model for the purpose of logic cell timing analysis in the presence of process variations is presented. A new current-based cell delay model is utilized, which can a...
A partial evaluator, given a program and a known "static" part of its input data, outputs a specialised or residual program in which computations depending only on the st...
Current logic synthesis techniques are ineffective for arithmetic circuits. They perform poorly for XOR-dominated circuits, and those with a high fan-in dependency between inputs ...
The behavior of reactive systems is typically speci ed by state machines. This results in an operational description of how a system its output. An alternative and more abstract ap...
Let C be a threshold logic circuit computing a Boolean function MODm : {0, 1}n → {0, 1}, where n ≥ 1 and m ≥ 2. Then C outputs “0” if the number of “1”s in an input ...