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ITC
2000
IEEE
110views Hardware» more  ITC 2000»
13 years 12 months ago
Algorithm level re-computing with shifted operands-a register transfer level concurrent error detection technique
—This paper presents Algorithm-level REcomputing with Shifted Operands (ARESO), which is a new register transfer (RT) level time redundancy-based concurrent error detection (CED)...
Ramesh Karri, Kaijie Wu
DFT
1997
IEEE
93views VLSI» more  DFT 1997»
13 years 11 months ago
An IDDQ Sensor for Concurrent Timing Error Detection
Abstract— Error control is a major concern in many computer systems, particularly those deployed in critical applications. Experience shows that most malfunctions during system o...
Christopher G. Knight, Adit D. Singh, Victor P. Ne...
IEEEPACT
2006
IEEE
14 years 1 months ago
Self-checking instructions: reducing instruction redundancy for concurrent error detection
With reducing feature size, increasing chip capacity, and increasing clock speed, microprocessors are becoming increasingly susceptible to transient (soft) errors. Redundant multi...
Sumeet Kumar, Aneesh Aggarwal
VTS
2003
IEEE
87views Hardware» more  VTS 2003»
14 years 26 days ago
An Analog Checker with Dynamically Adjustable Error Threshold for Fully Differential Circuits
We present a novel analog checker that adjusts dynamically the error threshold to the magnitude of its input signals. We demonstrate that this property is crucial for accurate con...
Haralampos-G. D. Stratigopoulos, Yiorgos Makris
AUSAI
2003
Springer
14 years 25 days ago
Choosing Learning Algorithms Using Sign Tests with High Replicability
An important task in machine learning is determining which learning algorithm works best for a given data set. When the amount of data is small the same data needs to be used repea...
Remco R. Bouckaert