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ISSS
1999
IEEE
151views Hardware» more  ISSS 1999»
13 years 12 months ago
Optimized System Synthesis of Complex RT Level Building Blocks from Multirate Dataflow Graphs
In order to cope with the ever increasing complexity of todays application specific integrated circuits, a building block based design methodology is established. The system is co...
Jens Horstmannshoff, Heinrich Meyr
ISPD
1998
ACM
101views Hardware» more  ISPD 1998»
13 years 12 months ago
Greedy wire-sizing is linear time
—The greedy wire-sizing algorithm (GWSA) has been experimentally shown to be very efficient, but no mathematical analysis on its convergence rate has ever been reported. In this...
Chris C. N. Chu, D. F. Wong
PADS
1998
ACM
13 years 12 months ago
Fault-Tolerant Distributed Simulation
In traditional distributed simulation schemes, entire simulation needs to be restarted if any of the participating LP crashes. This is highly undesirable for long running simulati...
Om P. Damani, Vijay K. Garg
SMILE
1998
Springer
13 years 12 months ago
Automatic 3D Model Construction for Turn-Table Sequences
As virtual worlds demand ever more realistic 3D models, attention is being focussed on systems that can acquire graphical models from real objects. This paper describes a system wh...
Andrew W. Fitzgibbon, Geoffrey Cross, Andrew Zisse...
MICRO
1997
IEEE
79views Hardware» more  MICRO 1997»
13 years 12 months ago
On High-Bandwidth Data Cache Design for Multi-Issue Processors
Highly aggressive multi-issue processor designs of the past few years and projections for the next decade require that we redesign the operation of the cache memory system. The nu...
Jude A. Rivers, Gary S. Tyson, Edward S. Davidson,...