3 search results - page 1 / 1 » Wire Sizing Alternative - An Uniform Dual-rail Routing Archi... |
DATE
2008
IEEE
14 years 1 months ago
2008
IEEE
To achieve minimum signal propagation delay, the nonuniform wire width routing architecture has been widely used in modern VLSI design. The non-uniform routing architecture exploi...
DATE
2009
IEEE
14 years 1 months ago
2009
IEEE
Abstract—To deal with the “memory wall” problem, microprocessors include large secondary on-chip caches. But as these caches enlarge, they originate a new latency gap between...
FPGA
2003
ACM
14 years 1 days ago
2003
ACM
How does multilevel metalization impact the design of FPGA interconnect? The availability of a growing number of metal layers presents the opportunity to use wiring in the thirddi...