94 search results - page 4 / 19 » Wire width planning for interconnect performance optimizatio... |
ISCAS
1995
IEEE
13 years 11 months ago
1995
IEEE
We present a novel technique for datapath allocation, which incorporates interconnection area and delay estimates based on dynamic oorplanning. In this approach, datapath area is ...
ASPDAC
2006
ACM
14 years 1 months ago
2006
ACM
—For nanoscale interconnection, the scattering effect will soon become prominent due to scaling. It will increase the effective resistivity and thus interconnection delay signifi...
GLVLSI
2007
IEEE
13 years 7 months ago
2007
IEEE
Given a set of placed blocks, we present an algorithm that minimally spaces the blocks to ensure routability under several assumptions. By performing a binary search on total widt...
DAC
1999
ACM
13 years 11 months ago
1999
ACM
As the CMOS technology enters the deep submicron design era, the lateral inter-wire coupling capacitance becomes the dominant part of load capacitance and makes RC delay on the bu...
ICCD
2002
IEEE
14 years 4 months ago
2002
IEEE
High performance SoC requires nonblocking interconnections between an array of processors built on one chip. With the advent of deep sub-micron technologies, switches are becoming...