94 search results - page 5 / 19 » Wire width planning for interconnect performance optimizatio... |
SLIP
2005
ACM
14 years 27 days ago
2005
ACM
The interconnection architecture of FPGAs such as switches dominates performance of FPGAs. Three-dimensional integration of FPGAs overcomes interconnect limitations by allowing in...
DATE
2003
IEEE
14 years 19 days ago
2003
IEEE
We propose a new metric for evaluation of interconnect architectures. This metric is computed by optimal assignment of wires from a given wire length distribution (WLD) to a given...
DAC
2007
ACM
14 years 8 months ago
2007
ACM
In this paper, we propose TROY, the first track router with yield-driven wire planning to optimize yield loss due to random defects. As the probability of failure (POF) computed f...
MICRO
2007
IEEE
14 years 1 months ago
2007
IEEE
A significant part of future microprocessor real estate will be dedicated to L2 or L3 caches. These on-chip caches will heavily impact processor performance, power dissipation, a...
ISPD
1997
ACM
13 years 11 months ago
1997
ACM
Advances in fabrication technology have resulted in a continual shrinkage of device dimensions. This has resulted in smaller device delays, greater resistance along interconnect w...