564 search results - page 112 / 113 » Wireplanning in logic synthesis |
ASPDAC
2007
ACM
13 years 11 months ago
2007
ACM
Abstract-- SAT sweeping is the process of merging two or more functionally equivalent nodes in a circuit by selecting one of them to represent all the other equivalent nodes. This ...
ISSTA
2010
ACM
13 years 11 months ago
2010
ACM
In program debugging, finding a failing run is only the first step; what about correcting the fault? Can we automate the second task as well as the first? The AutoFix-E tool au...
GLVLSI
2009
IEEE
13 years 11 months ago
2009
IEEE
Recent technology mappers for LUT based FPGAs employ cut enumeration. Although many cuts are often needed to nd good network, enumerating all cuts with large size consumes run-tim...
FPGA
1995
ACM
13 years 11 months ago
1995
ACM
In this paper, we present an improvement of the FlowMap algorithm, named CutMap, which combines depth and area minimization in the mapping process by computing min-cost min-height...
CAV
2008
Springer
13 years 9 months ago
2008
Springer
We present CSIsat, an interpolating decision procedure for the quantifier-free theory of rational linear arithmetic and equality with uninterpreted function symbols. Our implementa...