564 search results - page 11 / 113 » Wireplanning in logic synthesis |
GLVLSI
2006
IEEE
14 years 2 months ago
2006
IEEE
Most of the logic synthesis algorithms are not scalable for large networks and, for this reason, partitioning is often applied. However traditional mincut-based partitioning techn...
ASPDAC
2005
ACM
13 years 10 months ago
2005
ACM
It has been shown that Binary Decision Diagram (BDD) based logic synthesis enjoys faster runtime than the classic logic synthesis systems based on Sum of Product (SOP) form. Howev...
ICCAD
1991
IEEE
13 years 12 months ago
1991
IEEE
As feature sizes decrease and chip sizes increase, the area and performance of chips become dominated by the interconnect. In spite of this trend, most existing synthesis systems ...
LOPSTR
2000
Springer
13 years 12 months ago
2000
Springer
In this paper we will present a formal framework, based on the notion of extraction calculus, which has been successfully applied to define procedures for extracting information fr...
DAC
2012
ACM
11 years 10 months ago
2012
ACM
In this paper we introduce Chisel, a new hardware construction language that supports advanced hardware design using highly parameterized generators and layered domain-specific h...