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» Wireplanning in logic synthesis
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ICCAD
1995
IEEE
88views Hardware» more  ICCAD 1995»
13 years 12 months ago
LOT: logic optimization with testability-new transformations using recursive learning
: A new approach to optimize multi-level logic circuits is introduced. Given a multi-level circuit, the synthesis method optimizes its area, simultaneously enhancing its random pat...
Mitrajit Chatterjee, Dhiraj K. Pradhan, Wolfgang K...
DATE
2000
IEEE
124views Hardware» more  DATE 2000»
14 years 25 days ago
On the Generation of Multiplexer Circuits for Pass Transistor Logic
Pass Transistor Logic has attracted more and more interest during last years, since it has proved to be an attractive alternative to static CMOS designs with respect to area, perf...
Christoph Scholl, Bernd Becker
ASPDAC
2009
ACM
152views Hardware» more  ASPDAC 2009»
14 years 2 months ago
A novel Toffoli network synthesis algorithm for reversible logic
—Reversible logic studies have promising potential on energy lossless circuit design, quantum computation, nanotechnology, etc. Reversible logic features a one-to-one input outpu...
Yexin Zheng, Chao Huang
WWW
2009
ACM
14 years 9 months ago
Automated synthesis of composite services with correctness guarantee
In this paper, we propose a novel approach for composing existing web services to satisfy the correctness constraints to the design, including freeness of deadlock and unspecified...
Ting Deng, Jinpeng Huai, Xianxian Li, Zongxia Du, ...
GLVLSI
2003
IEEE
194views VLSI» more  GLVLSI 2003»
14 years 1 months ago
RF CMOS circuit optimizing procedure and synthesis tool
In this paper, we discuss a methodology to design and synthesize analog CMOS components such as RF amplifiers. The inputs of the synthesis tool are the circuit specifications desc...
Chandrasekar Rajagopal, Karthik Sridhar, Adrian Nu...