564 search results - page 22 / 113 » Wireplanning in logic synthesis |
ICCAD
1998
IEEE
14 years 20 days ago
1998
IEEE
The intellectual property (IP) business model is vulnerable to a number of potentially devastating obstructions, such as misappropriation and intellectual property fraud. We propo...
FPL
2004
Springer
14 years 1 months ago
2004
Springer
This paper describes the synthesis of dynamic differential logic to increase the resistance of FPGAs against Differential Power Analysis. Compared with an existing technique, it sa...
SAT
2007
Springer
14 years 2 months ago
2007
Springer
SAT solvers are often challenged with very hard problems that remain unsolved after hours of CPU time. The research community meets the challenge in two ways: (1) by improving the ...
ASPDAC
2008
ACM
13 years 10 months ago
2008
ACM
Scaling is currently the most popular technique used to improve performance metrics of CMOS circuits. This cannot go on forever because the properties that are responsible for the ...
VLSID
2002
IEEE
14 years 8 months ago
2002
IEEE
In this paper, we address the problem of power dissipation minimization in combinational circuits implemented using pass transistor logic (PTL). We transform the problem of power ...